1. Field of the Invention
The present invention relates to an address generation apparatus applicable to an operation system and a reconfigurable operation apparatus to which this address generation apparatus is applied.
2. Description of the Related Art
A general operation system has, for example, a CPU, an address generation apparatus, a plurality of configuration information memory and a reconfigurable operation apparatus.
In this operation system, a selection of a plurality of the configuration information memory is controlled by using the CPU.
In this case, the selection of the memory is performed by using the CPU during the period that the address generation apparatus generates an address.
In a DSP and so on in the related art, an address pattern to be generated is limited to a simple pattern such as for a loop of the C language. When performing a complex access, an address generated automatically was insufficient and it was necessary to perform the address calculation by using, for example, an ALU of the DSP.
Therefore a, cycle number necessary for the processing is more inefficient than that of the automatic address generation.
For improving this, an address generation apparatus using, for example, a counter has been proposed (refer to Japanese Unexamined Patent Publication (Kokai) No. 2002-215388).